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a microchip technology company ?2011 silicon storage technology, inc. ds25034a 09/11 data sheet www.microchip.com features ? organized as 256k x16 ? single voltage read and write operations ? 1.65-1.95v ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption (typical values at 5 mhz) ? active current: 5 ma (typical) ? standby current: 5 a (typical) ? sector-erase capability ? uniform 2 kword sectors ? block-erase capability ? uniform 32 kword blocks ? fast read access time ?70ns ? latched address and data ? fast erase and word-program ? sector-erase time: 36 ms (typical) ? block-erase time: 36 ms (typical) ? chip-erase time: 140 ms (typical) ? word-program time: 28 s (typical) ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bit ? data# polling ? cmos i/o compatibility ? jedec standard ? flash eeprom pinouts and command sets ? packages available ? 48-ball tfbga (6mm x 8mm) ? 48-ball wfbga (4mm x 6mm) micro-package ? 48-ball xflga (4mm x 6mm) micro-package ? all devices are rohs compliant 4 mbit (x16) multi-purpose flash SST39WF400B the SST39WF400B is a 256k x16 cmos multi-purpose flash (mpf) manufac-tured with proprietary, high-performance cmos superflash technology. the split- gate cell design and thick-oxide tunneling injector attain better reliability and man- ufacturability compared to alternate approaches. the SST39WF400B writes (pro- gram or erase) with a 1.65-1.95v power supply. this device conforms to jedec standard pin assignments for x16 memories. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 2 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company product description the SST39WF400B is a 256k x16 cmos multi-purpose flash (mpf) manufactured with sst proprie- tary, high-performance cmos superflash technology. the split-gate cell design and thick-oxide tun- neling injector attain better reliability and manufacturability compared to alternate approaches. the SST39WF400B writes (program or erase) with a 1.65-1.95v power supply. this device conforms to jedec standard pin assignments for x16 memories. the SST39WF400B features high-performance word-programming which provides a typical word- program time of 28 sec. it uses toggle bit or data# polling to detect the completion of the program or erase operation. on-chip hardware and software data protection schemes protect against inadvertent writes. designed, manufactured, and tested for a wide spectrum of applications, the SST39WF400B is offered with a guaranteed typical endurance of 100,000 cycles. data retention is rated at greater than 100 years. the SST39WF400B is suited for applications that require convenient and economical updating of pro- gram, configuration, or data memory. for all system applications, this mpf significantly improves per- formance and reliability, while lowering power consumption. it inherently uses less energy during erase and program than alternative flash technologies. when programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. for any given voltage range, superflash technology uses less current to program and has a shorter erase time; therefore, the total energy consumed during any erase or program operation is less than alternative flash tech- nologies. these devices also improve flexibility while lowering the cost for program, data, and configu- ration storage applications. superflash technology provides fixed erase and program times independent of the number of erase/ program cycles that have occurred. consequently, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/program cycles. to meet surface mount requirements, the SST39WF400B is offered in 48-ball tfbga, 48-ball wfbga, and a 48-ball xflga packages. see figures 2 and 3 for pin assignments and table 1 for pin descriptions. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 3 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company block diagram figure 1: functional block diagram y-decoder i/o buffers and data latches 1370 b1.0 address buffer latches x-decoder dq 15 -dq 0 memory address oe# ce# we# superflash memory control logic downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 4 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company pin assignments figure 2: pin assignments for 48-ball wfbga and 48-ball xflga figure 3: pin assignments for 48-ball tfbga a2a1 a0 ce# v ss a4a3 a5 dq8 oe# dq0 a6a7 nc dq10 dq9dq1 a17 ncnc dq2 nc dq3 nc v dd we# dq12 ncnc nc dq13 a9 a10 a8 dq4dq5 dq14 a11a13 a12 dq11 dq6 dq15 a14a15 a16 dq7 v ss top view (balls facing down) ab c d e f g h j k l 65 4 3 2 1 1370 48-wfbga m2q p02.0 SST39WF400B 1370 48-tfbga p01.0 SST39WF400B top view (balls facing down) 65 4 3 2 1 abcdefgh a13 a9 we# nc a7a3 a12 a8 ncnc a17 a4 a14a10 ncnc a6a2 a15a11 ncnc a5a1 a16 dq7dq5 dq2 dq0 a0 nc dq14dq12 dq10 dq8 ce# dq15dq13 v dd dq11 dq9 oe# v ss dq6dq4 dq3 dq1 v ss downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 5 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company table 1: pin description symbol pin name functions a ms 1 -a 0 1. a ms = most significant address a ms =a 17 for SST39WF400B address inputs to provide memory addresses. during sector-erase a ms -a 11 address lines will select the sector. during block-erase a ms -a 15 address lines will select the block. dq 15 -dq 0 data input/output to output data during read cycles and receive input data during program cycles. data is internally latched during a program cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the program operations. v dd power supply to provide power supply voltage: 1.65-1.95v for SST39WF400B v ss ground nc no connection unconnected pins. t1.0 25034 downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 6 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company device operation commands, which are used to initiate the memory operation functions of the device, are written to the device using standard microprocessor write sequences. a command is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. read the read operation of the SST39WF400B is controlled by ce# and oe#; both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high imped- ance state when either ce# or oe# is high. see figure 5. word-program operation the SST39WF400B is programmed on a word-by-word basis. the sector where the word exists must be fully erased before programming. programming is accomplished in three steps: 1. load the three-byte sequence for software data protection. 2. load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. 3. initiate the internal program operation after the rising edge of the fourth we# or ce#, whichever occurs first. once initiated, the program operation will be completed within 40 s. see figures 6 and 7 for we# and ce# controlled program operation timing diagrams and figure 18 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the inter- nal program operation, the host is free to perform additional tasks. any commands issued during the internal program operation are ignored. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 7 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company sector-/block-erase operation the SST39WF400B offers both sector-erase and block-erase modes which allow the system to erase the device on a sector-by-sector, or block-by-block, basis. the sector architecture is based on an uniform sector size of 2 kword. initiate the sector-erase oper- ation by executing a six-byte command sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the block-erase mode is based on an uniform block size of 32 kword. initiate the block-erase opera- tion by executing a six-byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase operation can be determined using either data# polling or toggle bit methods. see figures 11 and 12 for timing waveforms. any commands issued during the sector- or block-erase operation are ignored. chip-erase operation the SST39WF400B provides a chip-erase operation, which allows the user to erase the entire mem- ory array to the ?1? state. this is useful when the entire device must be quickly erased. initiate the chip-erase operation by executing a six-byte command sequence with chip-erase com- mand (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. dur- ing the erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 10 for the timing diagram, and figure 21 for the flowchart. any commands issued during the chip-erase operation are ignored. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 8 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company write operation status detection to optimize the system write cycle time, the SST39WF400B provides two software means to detect the completion of a program or erase write cycle. the software detection includes two status bits?data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the completion of the nonvolatile write is asynchronous with the system; therefore, either a data# polling or toggle bit read may occur simultaneously with the completion of the write cycle. if this occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . to prevent spurious rejection in the event of an erroneous result, the software routine must include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. data# polling (dq 7 ) when the SST39WF400B is in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is complete, dq 7 will produce true data. although dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid. valid data on the entire data bus will appear in subse- quent successive read cycles after an interval of 1 s . during an internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is complete, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block-, or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 8 for data# polling timing diagram and figure 19 for a flowchart. toggle bit (dq 6 ) during the internal program or erase operation, any consecutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between ?1? and ?0?. when the program or erase operation is complete, the dq 6 bit will stop toggling and the device is ready for the next operation. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 9 for toggle bit timing diagram and figure 19 for a flowchart. data protection the SST39WF400B provides both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd p o w er up/do wn detection: the write operation is inhibited when v dd is less than 1.0v. wr ite inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this pre- vents inadvertent writes during power-up or power-down. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 9 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company software data protection (sdp) the SST39WF400B provides the jedec approved software data protection scheme for all data alter- ation operations, i.e., program and erase. any program operation requires the inclusion of the three- byte sequence. the three-byte load sequence is used to initiate the program operation, providing opti- mal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. this group of devices are shipped with the software data protection permanently enabled. see table 4 for the specific software com- mand codes. during sdp command sequence, invalid commands will abort the device to read mode within t rc . the contents of dq 15 -dq 8 can be v il or v ih , but no other value, during any sdp command sequence. common flash memory interface (cfi) the SST39WF400B contains the cfi information that describes the characteristics of the device, and supports both the original sst cfi query mode implementation for compatibility with existing sst devices, as well as the general cfi query mode. to enter the sst cfi query mode, the system must write the three-byte sequence, same as the prod- uct id entry command, with 98h (cfi query command) to address 5555h in the last byte sequence. to enter the general cfi query mode, the system must write a one-byte sequence using the entry command with 98h to address 55h. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 5 through 7. the system must write the cfi exit command to return to read mode from the cfi query mode. product identification the product identification mode identifies the device as the SST39WF400B and the manufacturer as sst. this mode is accessed by software operations. use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see table 4 for software operation, figure 13 for the software id entry and read timing diagram, and figure 20 for the software id entry command sequence flowchart. table 2: product identification table address data manufacturer?s id 0000h 00bfh device id SST39WF400B 0001h 272eh t2.0 25034 downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 10 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company product identification mode exit/cfi mode exit to return to the standard read mode, exit the software product identification mode by issuing the soft- ware id exit command sequence. the software id exit command can reset the SST39WF400B to the read mode after an inadvertent transient condition that causes the device to behave abnormally. the software id exit/cfi exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 15 for timing waveform, and figure 20 for a flowchart. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 11 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company operations table 3: operation modes selection mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector or block address, xxh for chip-erase standby v ih x x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 4 t3.0 25034 table 4: software command sequence commandsequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 1. address format a 14 -a 0 (hex), addresses a ms- a 15 can be v il or v ih , but no other value, for the command sequence. a ms = most significant address a ms =a 17 for SST39WF400B data 2 2. dq 15 -dq 8 can be v il or v ih , but no other value, for the command sequence addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 5555h aah 2aaah 55h 5555h a0h wa 3 3. wa = program word address data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 4. sa x for sector-erase; uses a ms -a 11 address lines ba x for block-erase; uses a ms -a 15 address lines 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x 4 50h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 5,6 5. the device does not remain in software product id mode if powered down. 6. with a ms -a 1 = 0; sst manufacturer?s id = 00bfh, is read with a 0 =0, SST39WF400B device id = 272eh, is read with a 0 =1. 5555h aah 2aaah 55h 5555h 90h sst cfi query entry 5 5555h aah 2aaah 55h 5555h 98h general cfi query mode 55h 98h software id exit 7 / cfi exit 7. both software id exit operations are equivalent xxh f0h software id exit 7 / cfi exit 5555h aah 2aaah 55h 5555h f0h t4.0 25034 downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 12 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company table 5: cfi query identification string 1 for SST39WF400B address data data 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0001h primary oem command set 14h 0007h 15h 0000h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t5.0 25034 1. refer to cfi publication 100 for more details. table 6: system interface information for SST39WF400B address data data 1bh 0016h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0020h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min (00h = no v pp pin) 1eh 0000h v pp max (00h = no v pp pin) 1fh 0005h typical time out for word-program 2 n s (2 5 =32s) 20h 0000h typical time out for min size buffer program 2 n s (00h = not supported) 21h 0005h typical time out for individual sector/block-erase 2 n ms (2 5 =32 ms) 22h 0007h typical time out for chip-erase 2 n ms (2 7 = 128 ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x2 5 = 64 s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x2 5 =64ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x2 7 = 256 ms) t6.0 25034 downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 13 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company table 7: device geometry information for SST39WF400B address data data 27h 0013h device size = 2 n byte (0013h = 19; 2 19 = 512 kbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of byte in multi-byte write = 2 n (0000h = not supported) 2bh 0000h 2ch 0002h number of erase sector/block sizes supported by device 2dh 007fh sector information ( y+1= number of sectors ; z x 256b = sector size) 2eh 0000h y +1 = 12 7+1=128 sectors (007fh = 127) 2fh 0010h 30h 0000h z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) 31h 0007h block information ( y+1= number of blocks ; z x 256b = block size) 32h 0000h y+1=7+1=8blocks (0007h = 7) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t7.1 25034 downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 14 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company electrical specifications absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating con- ditions may affect device reliability.) temperature under bias ............................................. -55c to +125c storage temperature ................................................ -65c to +150c d. c. voltage on any pin to ground potential ............................ -0.5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential .................. -2.0v to v dd +2.0v voltage on a 9 pin to ground potential ...................................... -0.5v to 11v package power dissipation capability (t a = 25c) .................................. 1.0w surface mount solder reflow temperature ........................... 260c for 10 seconds output short circuit current 1 .................................................. 50ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. table 8: operating range range ambient temp v dd commercial 0c to +70c 1.65-1.95v industrial -40c to +85c 1.65-1.95v t8.1 25034 table 9: ac conditions of test 1 1. see figures 16 and 17 input rise/fall time output load 5ns c l =30pf t9.1 25034 downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 15 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company power-up specifications all functionalities and dc specifications are specified for a v dd ramp rate faster than 1v per 100 ms (0v to 1.8v in less than 180 ms). in addition, a v dd ramp rate slower than 1v per 20 s is recom- mended. see table 10 and figure 4 for more information. figure 4: power-up reset diagram table 10: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. v dd min to read operation 100 s t pu-write 1 v dd min to write operation 100 s t10.0 25034 1370 f37.1 v dd ce# t pu-read v dd min 0v downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 16 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company dc characteristics table 11: dc operating characteristics, v dd = 1.65-1.95v 1 1. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperature), and v dd = 1.8v. not 100% tested. symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht, at f=5 mhz, v dd =v dd max read 15 ma ce#=v il , oe#=we#=v ih , all i/os open program and erase 20 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 2 2. 40 a is the maximum i sb for all SST39WF400B commercial grade devices. 40 a is the maximum i sb for all SST39WF400B industrial grade devices. for all SST39WF400B commercial and industrial devices, i sb typical is 5 a. 40 a ce#=v dd ,v dd =v dd max i li input leakage current 1 a v in =gnd to v dd ,v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd ,v dd =v dd max v il input low voltage 0.2v dd v dd =v dd min v ih input high voltage 0.8v dd vv dd =v dd max v ol output low voltage 0.1 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.1 v i oh =-100 a, v dd =v dd min t11.0 25034 table 12: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. i/o pin capacitance v i/o =0v 12pf c in 1 input capacitance v in =0v 6pf t12.0 25034 table 13: reliability characteristics symbol parameter minimum specification units test method n end 1,2 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. n end endurance rating is qualified as a 10,000 cycle minimum for the whole device. a sector- or block-level rating would result in a higher minimum specification. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lth 1 latch up 100 + i dd ma jedec standard 78 t13.0 25034 downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 17 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company ac characteristics table 14: read cycle timing parameters symbol parameter 70 ns units min max t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 40 ns t ohz 1 oe# high to high-z output 40 ns t oh 1 output hold from address change 0 ns t14.0 25034 table 15: program/erase cycle timing parameters symbol parameter min max units t bp word-program time 40 s t as address setup time 0 ns t ah address hold time 50 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 50 ns t wp we# pulse width 50 ns t wph 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 50 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 50 ms t be block-erase 50 ms t sce chip-erase 200 ms t15.0 25034 downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 18 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company figure 5: read cycle timing diagram figure 6: we# controlled program cycle timing diagram 1370 f03.0 address a ms-0 dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data va l i d data va l i d t ohz note: a ms = most significant address a ms =a 17 for SST39WF400B 1370 f04.0 address a ms-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp note: a ms = most significant address a ms =a 17 for SST39WF400B x can be v il or v ih, but no other value. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 19 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company figure 7: ce# controlled program cycle timing diagram figure 8: data# polling timing diagram 1370 f05.0 address a ms-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# ce# t bp note: a ms = most significant address a ms =a 17 for SST39WF400B x can be v il or v ih, but no other value. 1370 f06.0 address a ms-0 dq 7 data data # data # data we# oe# ce# t oeh t oe t ce t oes note: a ms = most significant address a ms =a 17 for SST39WF400B downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 20 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company figure 9: toggle bit timing diagram figure 10: we# controlled chip-erase timing diagram 1370 f07.0 address a ms-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant address a ms =a 17 for SST39WF400B 1370 f08.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-erase operation the we# and ce# signals are inter- changeable as long as minimum timings are met. (see table 15) a ms = most significant address a ms =a 17 for SST39WF400B x can be v il or v ih, but no other value. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 21 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company figure 11: we# controlled block-erase timing diagram figure 12: we# controlled sector-erase timing diagram 1370 f09.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# ce# six-byte code for block-erase t be t wp note: this device also supports ce# controlled block-erase operation the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 15) a ms = most significant address a ms =a 17 for SST39WF400B x can be v il or v ih, but no other value. 1370 f10.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# controlled sector-erase operation the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 15) a ms = most significant address a ms =a 17 for SST39WF400B x can be v il or v ih, but no other value. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 22 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company figure 13: software id entry and read figure 14: sst cfi query entry and read 1370 f11.0 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: device id = 272fh for SST39WF400B x can be v il or v ih, but no other value. 1370 f12.0 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 oe# ce# three-byte sequence for sst cfi query entry t wp t wph t aa xx55 xxaa xx98 note: x can be v il or v ih, but no other value. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 23 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company figure 15: software id exit/cfi exit figure 16: ac input/output reference waveforms figure 17: a test load example 1370 f13.0 address a 14-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: x can be v il or v ih, but no other value. 1370 f14.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (v dd ) for a logic ?1? and v ilt (v ss ) for a logic ?0?. measure- ment reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times are (10% ? 90%) <5 ns. note: v it -v input test v ot -v output test v iht -v input high test v ilt -v input low test 1370 f15.0 to tester to dut c l v dd 25k 25k downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 24 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company figure 18: word-program algorithm 1370 f16.0 start load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xxa0h address: 5555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 25 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company figure 19: wait options 1370 f17.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data read dq 7 program/erase initiated program/erase initiated downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 26 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company figure 20: software id/cfi command flowcharts 1370 f18.0 load data: xxaah address: 5555h software id entry command sequence load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h cfi query entry command sequence load data: xx55h address: 2aaah load data: xx98h address: 5555h wait t ida read cfi data load data: xxaah address: 5555h software id exit/cfi exit command sequence load data: xx55h address: 2aaah load data: xxf0h address: 5555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation note: x can be v il or v ih , but no other value. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 27 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company figure 21: erase command sequence 1370 f19.0 load data: xxaah address: 5555h chip-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h load data: xxaah address: 5555h wait t sce chip erased to ffffh load data: xxaah address: 5555h sector-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x load data: xxaah address: 5555h wait t se sector erased to ffffh load data: xxaah address: 5555h block-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x load data: xxaah address: 5555h wait t be block erased to ffffh note: x can be v il or v ih , but no other value. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 28 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company product ordering information valid combinations for SST39WF400B SST39WF400B-70-4c-b3ke SST39WF400B-70-4i-b3ke SST39WF400B-70-4c-caqe SST39WF400B-70-4i-caqe SST39WF400B-70-4c-maqe SST39WF400B-70-4i-maqe note: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combi- nations. sst 39 wf 400b - 70 - 4c - b3ke xx xx xxxx - xx - xx - xxxx environmental attribute e 1 = non-pb package modifier k = 48 balls q = 48 balls (66 possible positions) package type b3 = tfbga ca = xflga ma = wfbga temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns device density 400 = 4 mbit voltage w = 1.65-1.95v product series 39 = multi-purpose flash 1. environmental suffix ?e? denotes non-pb sol- der. sst non-pb solder devices are ?rohs compliant?. downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 29 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company packaging diagrams figure 22: 48-ball thin-profile, fine-pitch ball grid array (tfbga) 6mm x 8mm sst package code: b3k a1 corner hgfedcba abcdefgh bottom view top view side view 65 4 3 2 1 65 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.10 0.45 0.05 (48x) a1 corner 8.00 0.10 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-5 note: 1. complies with jedec publication 95, mo-210, variant ab-1 , although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 30 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company figure 23: 48-ball extremely thin-profile, fine-pitch land grid array (xflga) 4mm x 6mm sst package code: caq lkjhgfedcba abcdefghjkl 65 4 3 2 1 65 4 3 2 1 0.50 0.50 bottom view 4.00 0.08 0.29 0.05 (48x) 6.00 0.08 2.50 5.00 a1 corner top view 48-xflga-caq-4x6-29mic-6.0 note: 1. complies with jedec publication 95, mo-207, variant czb-4, dimensions except the bump height is much less, and the a1 indicator is different. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.08 mm. 4. for low-profile mounting on pcb, sst recommends underfill for best solder joint reliability. 1mm detail side view seating plane 0.04 +0.025/-0.015 0.52 max. 0.473 nom. 0.08 a1 indicator downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 31 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company figure 24: 48-ball very-very-thin-profile, fine-pitch ball grid array (wfbga) 4mm x 6mm sst package code: maq lkjhgfedcba abcdefghjkl 65 4 3 2 1 65 4 3 2 1 0.50 0.50 bottom view 4.00 0.08 0.32 0.05 (48x) 6.00 0.08 2.50 5.00 a1 corner top view 48-wfbga-maq-4x6-32mic-2.0 note: 1. complies with jedec publication 95, mo-207, variant cb-4 except nominal ball size is larger and bottom side a1 indicator is triangle at corner. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.08 mm 4. ball opening size is 0.29 mm ( 0.05 mm) 1mm detail side view seating plane 0.20 0.06 0.73 max. 0.636 nom. 0.08 a1 indicator downloaded from: http:///
?2011 silicon storage technology, inc. ds25034a 09/11 32 4 mbit (x16) multi-purpose flash SST39WF400B data sheet a microchip technology company table 16: revision history revision description date 00 ? initial release of data sheet mar 2008 01 ? updated table 7 on page 13 jul 2008 02 ? eol of all d1qe and y1qe parts. replacements parts are the caqe and maqe in this document. ? added caqe and maqe package information. jan 2010 a ? applied new document format ? released document under the letter revision system ? updated spec number from s71370 to ds25034 sep 2011 ? 2011 silicon storage technology, inc?a microchip technology company. all rights reserved. sst, silicon storage technology, the sst logo, superflash, mtp, and flashflex are registered trademarks of silicon storage tech- nology, inc. mpf, sqi, serial quad i/o, and z-scale are trademarks of silicon storage technology, inc. all other trademarks and registered trademarks mentioned herein are the property of their respective owners. specifications are subject to change without notice. refer to www.microchip.com for the most recent documentation. for the most current package drawings, please see the packaging specification located at http://www.microchip.com/packaging. memory sizes denote raw storage capacity; actual usable capacity may be less. sst makes no warranty for the use of its products other than those expressly contained in the standard terms and conditions of sale. for sales office locations and information, please see www.microchip.com. silicon storage technology, inc. a microchip technology company www.microchip.com isbn:978-1-61341-450-7 downloaded from: http:///

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